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Specifications
All specifications are guaranteed unless noted otherwise. All specifications apply to all models unless noted otherwise.
General specifications
- Acquisition rate with frequency margin
- 8 GT/s (+5% to -10%)
5 GT/s (±10%)
1.5 GT/s (±10%)
- Number of lanes
-
- TLA7SA08
- 8 differential inputs, x4
- TLA7SA16
- 16 differential inputs, x8
- Record length
- 160 M symbols translates into 160 ms at 8 GT/s, 320 ms at 5 GT/s, or 640 ms at 2.5 GT/s at 100% bus utilization.
- TLA7SA08
- 160 M symbols per differential input, 4 GB physical memory total
- TLA7SA16
- 160 M symbols per differential input, 8 GB physical memory total (16 GB physical memory for a x16 configuration)
- Time stamp range
- 292 hours
- Time stamp
- 50 bits at 936 ps resolution
- Clocking/acquisition modes
-
- TLA module without SSC (spread spectrum clocking)
- External reference clock
- 100 MHz ±10% with or without SSC
- External reference clock frequency tolerance
- ±300 ppm
- Number of mainframe instrument slots required per TLA series module
- 2
Module configuration requirements
- Bi-directional link widths per module
-
Module X1 X4 X8 X16 TLA7SA08 1 1 0 0 TLA7SA16 1 1 1 2
Input specifications (with P67SA00 series probes)
- Capacitive loading
- Please refer to the specifications in the Tektronix Logic Analyzer Solutions for PCI Express 3.0 manual, Tektronix part number, 077-0400-xx.
- Minimum data eye
- Please refer to the specifications in the Tektronix Logic Analyzer Solutions for PCI Express 3.0 manual, Tektronix part number, 077-0400-xx.
Acquisition system (with P67SA00 series probes)
- Dynamic link width switch latency
- Consumes up to 48 symbols (typical)
- Dynamic link rate switch latency
- <200 ns EIDLE time (typical) (with either internal reference clock or spread spectrum using external reference clock)
- Maximum time to change to Gen1 rate
- 2 TS1
- Maximum time to change to Gen2 rate
- 1 EIEOS + 3 TS1
- Maximum time to change to Gen3 rate
- 1 EIEOS + 6 TS1
- Number of FTS packets required to resync following L0s exit
- Assumes an EIDLE ranging from 20 ns to 2 ms, with either internal reference clock or spread spectrum using external reference clock
- Gen1
- 4 FTS (typical)
- Gen2
- 1 EIEOS + 6 FTS (typical)
- Gen3
- 1 EIEOS + 4 FTS (typical)
Filter specifications
- Ordered sets
- TS1, TS2, SKP, EIOS, FTS, EIEOS, SDS
- DLLPs
- Ack, Nak, PM, Vendor specific, FC1, FC2, UpdateFC
- TLPs
- MRd, MRdL, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CPlLk, CPlDLk, FetchAdd, Swap, CAS, LPrfx, EPrfx
Trigger system
- Independent Trigger states
- 8
- Trigger sequence rate
- Operates at symbol rate time (Gen1, Gen2, Gen3)
- Maximum independent If/Then clauses per state
- 8
- Maximum number of events per If/Then clause
- 8
- Maximum number of actions per If/Then clause
- 8
- Maximum number of event counters per state
- 2
- Event counter range
- 31 bit
- Number of TLP packet recognizers per link direction
- 4
- Number of DLLP packet recognizers per link direction
- 4
- Number of sequence recognizers
- 4
- Number of symbols per sequence recognizer
- 16
- Number of link event recognizers
- 4
- Number of global counters/timers
- 4
- Trigger event types
- Anything, TLP, DLLP, Sequence, Link Event, Counter, Timer
- Trigger action types
- Trigger, Trigger All Modules, Wait for System Trigger, Goto, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Reset Timer, Reset and Start Timer, Stop Timer, Reset and Stop Timer, Set Signal Out, Clear Signal Out, Arm Module, Start Storage, Stop Storage, Do Nothing
- Counter/timer range
- 48 bit (~5 days with 3.6 ns resolution)
- Counter/timer test latency
- 68 ns
- Storage control (data qualification)
- By state (start/stop)
Physical characteristics
- Dimensions
-
- Height
- 262 mm (10.3 in.)
- Width
- 61 mm (2.4 in.)
- Depth
- 381 mm (15.0 in.)
- TLA7SA08 weight
-
- Net
- 2.84 kg (6.25 lb.)
- Shipping
- 6.94 kg (15.3 lb.)
- TLA7SA16 weight
-
- Net
- 3.20 kg (7.06 lb.)
- Shipping
- 7.30 kg (16.1 lb.)
PCI Express midbus differential data probes
- General
-
Characteristic P67SA08 P67SA16 P67SA16G2 Number of differential pairs 8 16 16 Lane width x4 x8 x8 Recommended use Recommended where signal integrity is critical Recommended where signal integrity is critical Recommended for midbus probing of PCIe Gen2 Attachment to target system Compression technology Compression technology - Probe loading AC/DC Refer to the Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction manual, Tektronix part number 077-0400-xx. Cable length 1.8 m (6 ft.)
- Midbus probe recommended configurations
-
x1 x4 x8 x16 1 P67SA08 1 TLA7SA08 1 P67SA08 1 TLA7SA08 1 P67SA16 1 TLA7SA16 2 P67SA16 2 TLA7SA16
PCI Express slot interposer probes
- General
-
Characteristic P67SA04S P67SA08S P67SA16S Number of differential pairs 8 16 32 Lane width x4 x8 x16 Recommended use Recommended for platforms with no midbus footprints and the PCI Express slot is the only probe access point Attachment to target system PCI Express slot Probe loading AC/DC Refer to the Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction manual, Tektronix part number 077-0400-xx. Cable length 1.8 m (6 ft.)
- Slot interposer probe recommended configurations
-
x1 x4 x8 x16 1 P67SA04S 1 TLA7SA08
1 013-0375-xx1 P67SA04S 1 TLA7SA08 1 P67SA08S 1 TLA7SA16 1 P67SA16S 2 TLA7SA16
PCI Express solder down and UHDSMA probes
- General
-
Characteristic P67SA01SD P67UHDSMA Probe type PCI Express differential solder-down probe Probe lead set for PCI Express P67SA00 series probe connections to high-bandwidth oscilloscopes Number of differential pairs 1 4 Lane width 1/2 lane x2 Recommended use Recommended for platforms with no midbus footprint, PCI Express slot; or where space is limited Recommended for use with any of the P67SA00 series probe connections to high-bandwidth oscilloscopes Attachment to target system Solder down - Probe loading AC/DC Refer to the Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction manual, Tektronix part number 077-0400-xx. - Cable length 1.8 m (6 ft.) 0.3 m (1 ft.)
- Solder-down probe recommended configuration
-
x1 x4 x8 x16 2 P67SA01SD 1 TLA7SA08 8 P67SA01SD 1 TLA7SA08 16 P67SA01SD 1 TLA7SA16 32 P67SA01SD 2 TLA7SA16