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Using the TMT4 Margin Tester's LTSSM Monitor for PCIe Device Testing

PCIe Device Testing with the LTSSM feature of the TMT4 Margin Tester

This application note describes how during PCI Express® device testing the information provided by the Tektronix TMT4 Margin Tester's Link Training Status State Machine (LTSSM) monitoring feature can be used.  The LTSSM monitor provides information about the various states achieved by the TMT4 Margin Tester as it interacts with the Device Under Test (DUT) without regard to its role as a Root Complex (RC) or End Point (EP). This advanced feature, together with the generation of hardware trigger-in/trigger-out capabilities, allows users to identify anomalies in the Physical Layer interaction with the Data Link Layer according to PCIe State Machine descriptions.

PCI Express, PCIE, and PCI-SIG are registered trademarks and/or service marks of PCI-SIG.