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Dealing with timing and bit errors has become a critical step in the process of developing optimal serial data system designs. Evolving design requirements call for more complex signal analysis, more intricate measurement needs, and more analysis of interactions between the transmitter and the channel.
This web-based seminar discusses the effect of clock jitter on serial data systems, the role it plays in both transmitters and receivers, and how simple models can be used to isolate the clock jitter that impacts the bit error rate (BER). In addition, it discusses how newer high speed serial data standards running on lossy/dispersive channels are using equalization (FFE/DFE) to open the eye diagram, leading to more predictive BER. Comparison of measurements at the receiver and the recommended measurements at the Transmitter are covered, as well as other SDLA concepts of interest to serial data designers and test engineers.
Serial Data Technical Marketing Manager, Tektronix, Inc.