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高速串行通信

下一代数字接口标准(串行、内存、显示等)会推动如今的一致性和诊断工具的限制,产生高速 Tx 和 Rx 设计挑战,包括:

  • 因设备体积较小而造成的有限信号访问
  • 具有新的节能方案的总线行为
  • 使用信号接口验证新的信号编码和均衡能力
  • 电子验证测试太多,时间太少!

泰克提供的自动测量套件可加快 PHY 验证周期,并保证一致性。当一致性测量未通过时,可使用协议解码、可视化触发等工具来加速调试。在来源中确定抖动和噪声,如串扰或其他多通道噪声耦合。

标准和技术

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Library

Title
MIPI Debug and Conformance Testing Challenges and Solutions
View the slides from the presentation, MIPI High Speed Serial Technologies: Debug & Conformance Testing Challenges and Solutions, created by Tektronix' Ramesh P.E, Principal Engineer and Parthasarathy …
PCI Express®发射机PLL测试 — 不同方法对比
根据使用的测试仪器类型,可以通过多种方法测量PLL环路响应。正如预期的那样,各种方法在测试精度、测试速度(吞吐量)、易用性、设置简便性和购买费用上各有优势和劣势。此外,某些方法存在局限性,不能广泛用于所有类型的PLL。尽管所有方法都可以测试是否满足规范要求,但某些方法为时钟设计人员优化设计提供了额外的实用信息。
检定16G光纤通道速率的SFP+收发机
研究根据16G光纤通道标准测试SFP+收发机所需的测量,同时覆盖多模850 nm接口和单模1310 nm接口。其中包括一个测试和检定实例,采用单模1310 nm激光器SFP+收发机及14.025 Gb/s的16G线速,同时采用一流的测试设备。
PCIe 5.0发射机验证
了解PCI Express 5.0的概况、测试以及与之相关的挑战,为您解读泰克PCIe 5.0传输器测试解决方案。
高速接口标准
本电子指引将帮助您进一步了解PCIe 4.0、SAS、SuperSpeed USB和DDR4标准测试时面临的设计挑战。在这本电子指引中,您还将快速获得许多技术资源,帮助您了解设计挑战,根据测试需求选择适当的解决方案。
PCI Express Gen5 Automated Multi-Lane Testing
Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple differential lanes for the link under …
为迎接DVI 一致性测量挑战提供快速高效的解决方案
泰克为您提供了所需的全部DVI测量解决方案,从高带宽数字荧光示波器(DPO)到探头、再到专用软件。泰克解决了许多棘手的测量问题,如抖动和眼图测试,提供了优秀的DVI解决方案,自动完成及简化您的工作。
远程探头采集改善高速串行测量
随着高速串行数据速率不断提高,使测量余量达到最大的需求也在提高。即使质量非常好的同轴电缆也会影响测量余量。示波器远程探头提供了明显的优势,可以使信号完整性测量的余量达到最大。
Probing Tips for High Performance Design and Measurement
When a high performance system or component needs to be verified, it often requires attaching an oscilloscope probe. For high speed circuits, the effect of attaching a probe often cannot be ignored …
Title
MIPI C-PHY D-PHY Webinar
MIPI alliance standards have been driving the adoption of newer features and higher data rates for emerging mobile applications.  Oscilloscope-based protocol layer validation enables isolating …
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation
PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
PCIe Gen6 PAM4 Signaling
Prepare for the next PCI Express inflection point by viewing this discussion of validation requirements for PCI Express Gen6.  We review newly introduced transmitter measurements including SNDR and …
DDR5 Memory Characterization
While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges.  Learn about characterization and …
PCIe Gen5 to Gen6 and Comparison to Electrical Ethernet
Watch as David Bouse explains the evolution of PCI Express from Gen5 to Gen6. Then hear from Pavel Zivny as he and David discuss PAM4 signaling in PCIe and how it compares with PAM4 as applied in …
Thunderbolt Compliance Test Setup Webinar
View our webinar, Choosing the Best Test Setup for Thunderbolt™️ Compliance Testing, and learn which test setup is best suited for your Thunderbolt 3 and Thunderbolt 4 design. 课件:Choosing the Best …
USB4 Webinar
View our USB4 Compliance and Characterization Test webinar to learn how you can address the measurement challenges associated with the new USB4 standard.
PCI Express Gen 5 Reference Clock Webinar
This webinar presents an overview of reference clock jitter requirements as they have evolved and offers techniques for making these low femtosecond measurements using a real time oscilloscope. 
DDR5 Test Challenges Webinar
Learn how you can address five of the thorniest measurement challenges associated with the new DDR5 standard. Get an update on the DDR5 Rx/Tx compliance test and insight in the latest characterization …
PCI Express Gen 5 Update Webinar
Cloud-based computing power, storage capacity, and network bandwidth have led to the development of the PCI Express 5.0 specification for 32.0 GT/s. This webinar starts with an overview of 5.0 …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation
This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test
During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers. You'll also get useful tips and technical insights into characterizing and …