PCI Express

PCI Express

通过泰克的测试解决方案,加快 PCIe 设计的分析、验证和预一致性测试。

利用适用于发射机和接收机测试的仪器和分析软件,我们的解决方案能够为当前和下一代规格的 PCIe(Gen 1、2、3 标准和当前 PCIe 4.0 标准)执行深入分析、一致性测试和调试。


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Title
克服第四代I/O应用中的接收机测试挑战

这份最新应用指南提供了重要信息,介绍了怎样使用误码率测试仪对第四代企业接收机执行一致性测试和诊断测试。

Logic Analyzer Fundamentals

Learn the basics and benefits of logic analyzers - see how this tool can solve your debug challenges.

Overcoming PCI-Express Physical Layer Challenges

Using the powerful triggering and multiple data views of the Tektronix Logic Protocol Analyzer to overcome physical layer challenges.

了解和表征定时抖动入门手册在采用电压跳变表示定时信息的所有电气系统中,定时抖动都是不受欢迎的伴生产物。本文主要介绍电系统中的抖动。
Hunting PCIE Flow Control Bugs

This white paper describes in detail the use of the Bird's Eye View (BEV), a completely new visualization, to investigate flow control.

触发基础知识-DPO7000、MSO/DPO/DSA70000系列示波器Pinpoint®/可视触发及高级搜索和标记技术

本文讨论了触发技术基础知识,以及Pinpoint触发与搜索和标记功能怎样把实时示波器中的触发技术提升到全新的水平。

PCI Express Probing Solutions with the Tektronix Protocol Analyzer

This white paper discusses how to ensure proper board design and layout for digital debug and verification using the Tektronix PCIe Protocol Analyzer.

PCI Express®发射机PLL测试 — 不同方法对比

概括了执行PLL测试的重要方法

串行数据一致性测试和验证测量基础知识

本入门手册旨在帮助您了解串行数据传输的常见方面,阐述了适用于这些新兴串行技术的模拟和数字测量要求。

迁移到第4代企业和数据中心I/O标准

此白皮书内容包括自适应均衡和链路训练、复杂测试前向纠错FEC的影响、调试协议握手和物理层问题,通道性能评估最新发展趋势和转变到第四代标准需要的材料。

Title
PCIe要了解的10件事

了解PCIe Gen4有哪些特点,一致性测试,包括校准、预置测试、自动化和调试;发射机和接收机测试程序;PCIe调试,包括环回初始化和协议识别握手。

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BSX-Series BERTScope TX测试演示

根据高达32 Gb/s的标准,迅速调试物理层和链路训练问题。化繁为简,满怀信心!

2:12

BSX-Series BERTScope在Gen 4 RX中

BSX-Series BERTScope在Gen 3 RX中

What‘s new for server storage testing?

标题
Understanding Differences between PCI Express 4.0/5.0 and IEEE High Speed Electrical Specifications

Our Tektronix domain experts, Dan Froelich and Pavel Zivny, contrast the methodologies of the PCI Express 4.0/5.0 and IEEE 26 GBd NRZ/PAM4 electrical specifications and engage in a lively discussion of the pros/cons of the approaches taken by each.

Addressing PCIe Gen1-5 Test and Debug Challenges with Confidence

Learn how to address the test and measurement challenges posed by PCIE Gen1-5 for both base silicon testing and CEM compliance testing. Gain insights and solutions for automation, validation, and debug for PCIE Gen1-5.

Getting to PCI Express Compliance Faster

This webinar will provide the information on test processes for PCIe devices to allow you to reach compliance faster.

Overcoming Challenges in PCI Express Compliance Testing

Learn the keys to debugging, verifying design and performing interoperability testing for PCI Express revisions 3.0 and 4.0.

Maximizing Margins for 4th Gen High Speed Serial Standards

As data rates increase, the effect of cables and fixtures become a larger part of the overall measurement result. Gain insight into the issues and how to solve them for each step of the signal path from the device under test to the oscilloscope.

从物理层到协议层、从一致性测试到故障排除,泰克全新PCIE解决方案帮助您化繁为简,为您提供全方位解决方案

本研讨会主要针对于从事电缆、连接器等设计和分析的工程师和技术人员。让大家在更好的理解TDR阻抗、S参数、眼图以及Active有源Cable测量技 术的基础上,着重介绍QSFP/SFP+、HDMI2.0、Thunderbolt、USB 3.0、DisplayPort等线缆最新测试规范和目前高频线缆发展趋势。

泰克应对下一代高速串行设计挑战技术讲座

当前第二代和第三代的高速串行数据标准如PCIE gen2(5G)、SATA gen3(6G)、XAUI gen2(6.25G),其数据速率已经达到5G或者更高。这样的高速信号在物理信道中传输时衰减非常严重,甚至造成信号眼图的闭合。如何才能保证接收端还能正确的接收到信号,这给设计人员带来了严重的挑战......

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PCIe Gen 4.0 Rx & Link Equalization Test Procedure MOI

This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 Rx and Link Equalization Test Procedures.

PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedure MOI

This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 CEM Add-in Card PLL Bandwidth Test Procedures.

PCIe Gen 4.0 TX CEM Test Procedure MOI

This document cover the Method of Implementation (MOI) for PCIe Gen 4.0 TX CEM Test Procedures.

PCIe Gen 3.0 Link Equalization System and Add-in Card Test Procedure

Tektronix PCI Express Gen3 Link EQ test MOI. This document cover Link EQ testing for both System DUT and Add-In Card.

PCI Express 3.0 PLL Test MOI for Add-In Cards

This document covers the Method of Implementation (MOI) for PCI Express 3.0 Phase-Lock-Loop (PLL) testing for Add-In Cards (AIC).

PCI Express 3.0 Card Transmitter Test MOI

This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM and U.2 card transmitter testing, using DPO70000 Series Oscilloscopes.

PCI Express 3.0 System Transmitter Test MOI

This document covers the Method of Implementation (MOI) for PCI Express 3.0 CEM and U.2 System transmitter testing, using DPO70000 Series Oscilloscopes.

PCI Express 3.0 Receiver Test MOI for BASE Spec

This document covers the Method of Implementation (MOI) for PCI Express 3.0 BASE receiver testing, using BERTScope instruments.

PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test MOI

This document covers the Method of Implementation (MOI) for PCIe Gen3 (8GT/s) Receiver Jitter Tolerance Test (Add-In Card and System) using Tektronix BSX Series BERTScope Bit Error Tester and ‘BERTScope PCIE3.0 Receiver Testing’ Application.

Methods of Implementation (MOI) for Verification+ Debug and Characterization

This document covers the Method of Implementation (MOI) for DPOJet measurements provided in the DPO70000 Option PCE, Option PCE3, and Option PCE4 solutions packages.

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